Commit 81d2c40c authored by Hsiang-Yu's avatar Hsiang-Yu
Browse files

Add all simulink models

parent 0b211de8
Pipeline #140 failed with stages
/opt/rtcds/rtscore/tags/advLigoRTS-2.8.8/src/epics/simLink
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/*
Long Pulse. When receives an input value different from the previous input value,
the output goes to that value and the c code begins a counter.
It will remain at that initial input value until the counter finishes.
If the input value changes after that time, it will immediately transition.
If the input value changes before the counter finishes, it will ignore it until the counter finishes.
Threshold defined by model rate (in Hz) and wait time (in seconds).
datIn[0] = Input
datIn[1] = WaitTime (how many seconds to wait after receiving a 1
before outputting a 1)
datOut[0] = long pulse of input
*/
void LONG_PULSE(double *datIn, int nIn, double *datOut, int nOut)
{
static int isFirst = 1;
double input;
double WaitTime;
double ModelRate;
static double counter;
double threshold;
static double previous_output;
static int finished_counting;
input = datIn[0];
WaitTime = datIn[1];
ModelRate = FE_RATE;
threshold = WaitTime * ModelRate;
if (isFirst) { // Initialize counter for first run
isFirst = 0;
counter = 0;
previous_output = input;
}
if (counter > threshold) {
finished_counting = 1;
}
if (finished_counting == 1) {
if (previous_output != input) {
previous_output = input;
finished_counting = 0;
counter = 0;
}
} else {
counter++;
}
datOut[0] = previous_output;
} // end of long_pulse()
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